This invention relates to the process of manufacture of MOSFET devices and more particularly to the method for manufacture of thin gate dielectric layers for high-performance MOSFET devices.
The scaling of gate dielectric layers to smaller thicknesses is one of the key elements that enables the continued scaling of silicon CMOS technology to higher performance levels. Thinner gate dielectric layers generate more inversion charge, which increases transistor drive current, and also improves short-channel effects by increasing gate control of the channel. Because the gate dielectric layer is formed at the interface where the inversion layer is formed and transistor current is conducted, this must be an extremely high quality interface.
Oxynitrides (SiOxNy) are now widely used in the semiconductor industry as gate dielectric films. The desired properties of gate dielectrics are low gate leakage current, high dielectric constant to increase capacitance, high mobility, high reliability and good diffusion barrier properties. Pure SiO2 has been the gate dielectric of choice since the early days of the integrated circuit, however, in recent years as gate dielectrics are being scaled into the sub 20 xc3x85 thickness range, oxynitrides have been increasingly used in high performance CMOS processes.
Silicon Oxynitrides (SiOxNy) are generated by two general techniques, thermal and plasma nitridation. Thermal nitridation of oxynitrides is carried out by high temperature exposure (650xc2x0 C.-1000xc2x0 C.) of a silicon surface, or silicon dioxide (SiO2) surface to a reactive nitrogen containing gas such as nitrous oxide (N(2O), ammonia (NH3), or nitrogen oxide (NO). Thermal energy is used to drive the nitridation reaction. Plasma nitridation of oxynitrides is performed by exposure of a silicon or SiO2 surface to an activated nitrogen containing plasma. Because the nitrogen has been activated by the plasma, it can react to be incorporated in the oxynitride at lower temperatures than thermal nitridation (anywhere from room temperature to 800xc2x0 C.). If the plasma nitridation process is performed at a low temperature (e.g.  less than 100xc2x0 C.), it can be compatible with a photoresist soft-mask process. In this type of low temperature process, the photoresist can be used to selectively block the nitridation from the covered areas, while the exposed areas receive the desired nitrogen incorporation. Thermal processes, as well as high temperature plasma process are not compatible with photoresist. Thermal processes require hard-masks that can withstand high temperatures. Photoresist soft-masking is particularly attractive because resist can be stripped using chemistries that are compatible with gate oxides (e.g. sulphuric acid/hydrogen peroxide (H2O2) mixtures).
Properly optimized oxynitrides have increased dielectric constants, lower gate leakage current, and improved diffusion barrier properties as compared to pure SiO2. FIG. 1 shows how the gate leakage current decreases with increasing the duration of processing when using a Remote Plasma Nitridation (RPN) process of forming oxynitrides. Often these improvements must be carefully balanced against changes in mobility that may affect the transistor device current. Moreover, this optimization may be different for NFET and PFET devices which reside on the same semiconductor chip. In FIG. 1, gate leakage in (amperes/cmxe2x88x922) at 1.2 Volts is shown as a function of T inv(xc3x85). The parameter Tinv is inversion thickness, which is a measure of the effective oxide thickness when the transistor is measured in inversion mode. Units are thickness such as angstroms (xc3x85) or nanometers (nm).
FIGS. 2-3 show examples of how plasma nitridation affects the PFET and NFET device drive current differently. These examples demonstrate that the optimum nitrogen concentration in the gate dielectric is different between the NFET and PFET device, which is generally not known. The vertical axis is Joff and the horizontal axis is Jodlin where Jodlin stands for transistor drain current density (Amperes/xcexcm), i.e. per unit width of the transistor between the source and the drain. It is a transistor current measured with Vg (gate voltage) a fixed amount above Vt (threshold voltage) to help normalize out any threshold voltage differences. The Joff is a measure of off-state leakage per unit width of the transistor (between the source and the drain) with 0 Volts applied to the gate electrode.
FIGS. 4A-4D are schematic conceptual diagrams wherein FIGS. 4A-4D are views of NFET area 14 and related features taken along section line A-Axe2x80x3 in FIG. 8A and PFET area 16 and related features taken along section line B-Bxe2x80x3 in FIG. 8A. FIGS. 4A-4D show juxtaposed PFET and NFET sectors of a semiconductor device 10 formed in a silicon substrate 12 in four steps of a prior art process, which illustrates how a standard sequence of processing steps of gate dielectric integration results in the same PFET and NFET oxynitride gate dielectric layers 18N/18P for the high-performance transistors with the thinnest gate dielectric layer. This is because when the thin gate dielectric layers 18N/18P are grown, both the NFET area 14 and the PFET area 16 in the substrate 12 are exposed to the same process. This is true whether the process is thermal-based or plasma-based, but a plasma process is shown for illustration.
In FIG. 4A, the device 10 is shown in an early stage of manufacture thereof comprising a silicon semiconductor substrate 12, which has been processed to contain both a P-doped NFET area 14 and an N-doped PFET area 16 in substrate 12.
In FIG. 4B, the device 10 of FIG. 4A is shown after a gate oxide layer 18N has been formed above the top surfaces of the NFET area 14 and gate oxide layer 18P has been formed above the top surfaces of the PFET area 16.
In FIG. 4C, the device 10 of FIG. 4B is shown after the gate oxide layers 18N/18P have been treated with a uniform plasma nitridation by driving nitrogen into the gate oxide layers 18N/19P above the top surfaces of the NFET area 14 and the P-doped PFET area 16. The same is true for a thermal nitridation.
In FIG. 4D, the device 10 of FIG. 4C is shown with the identical gate dielectric layers 18A in place of gate oxide layers 18N/18P. The identical gate dielectric layers 18A have been shaded with horizontal dash lines to show the transformation of the gate oxide layers 18N/18P into the identical gate dielectric layers 18A as a result of the uniform nitridation of the gate dielectric layers 18N/18P of FIG. 4C above the top surfaces of the NFET area 14 and the PFET area 16. Please note that FIG. 4D is composed of sections taken along lines A-Axe2x80x3 and B-Bxe2x80x3 in FIG. 8A.
Because the optimum oxynitride is different for NFET and PFET devices, it is highly desirable to optimize the two separately, since the overall CMOS integrated circuit performance is determined by both NFET and PFET device performance. If the same gate dielectric layers 18N/18P were grown over NFET area 14 and the PFET area 16 at the same time, one device will be optimized, while the other will be sub-optimum. The fact that there is a suboptimum device may limit the overall CMOS circuit performance of the product.
U.S. Pat. No. 6,093,661 of Trivedi et al entitled xe2x80x9cIntegrated Circuitry And Semiconductor Processing Method of Forming Field Effect Transistorsxe2x80x9d teaches nitrogen atom concentration peaking at any elevational location in the gate dielectric layers of the device, but preferably at a location in the gate dielectric layers proximate the lower interface between the gate dielectric layers and the P and N doped regions of a monocrystalline silicon semiconductor substrate. Preferably, the concentration of nitrogen atoms is from 0.1% to 10.0% molar in the peak elevation region in the gate dielectric layer, preferably from 0.5% to 5.0% molar, with a thickness for the peak elevation region from 30 xc3x85 to 60 xc3x85. Introduction of nitrogen into the gate dielectric layer can be done in a thermal processing furnace at a temperature from 750xc2x0 C. to 950xc2x0 C., ideally 850xc2x0 C. at atmospheric pressure, with nitrogen provided at about 100 to 10,000 sccm, ideally 1,000 sccm, from 5 minutes to 2 hours, ideally 30 minutes. The preferred sources of nitrogen atoms have an Nxe2x80x94xe2x80x94O bond because of the ease of breaking the nitrogen bonds. However, other sources can be used, such as nitrogen oxide (NO), nitrous oxide (N2O), ammonia (NH3), and nitrogen gas (N2). Otherwise Rapid Thermal Processing (RTP) introduces nitrogen atoms into the gate dielectric layer using one of the above nitrogen based compounds in a reactor heated to from about 800xc2x0 to 1200xc2x0 C. at atmospheric pressure with the temperature increasing at a rate from about 10xc2x0 C. per second to 200xc2x0 C. per second peaking at a time range of 10 seconds to 2 minutes. Alternatively nitrogen atoms are added to the gate dielectric layer using a nitrogen plasma treatment or a nitrogen ion implant. A goal of Trivedi et al is to produce Sixe2x80x94xe2x80x94N bonds at least partially along the lower interface. A preferred purpose of Trivedi et al for the lower interface region is to prevent subsequent outdiffusion of p-type material from a PFET transistor gate layer (which is p-doped with boron) into a transistor channel. Another purpose of Trivedi et al is to restrict of further oxidation of the gate dielectric layer during later processing of the semiconductor substrate. Trivedi et al describes an optional further thermal processing of the semiconductor substrate performed after forming the nitrogen region to re-oxidize the gate dielectric layer. An example of such a reoxidation process is at 900xc2x0 C. in pure N2 at 1,000 sccm, O2 at 6,000 sccm, N2 at 50 sccm and employs a chlorine source gas at 50 sccm for a period of 50 minutes. Related patents included U.S. Pat. No. 6,417,546 of Trivedi et al entitled xe2x80x9cP-Type FET in a CMOS with Nitrogen Atoms in the Gate Dielectricxe2x80x9d and U.S. Pat. No. 6,541,395 of Trivedi et al entitled xe2x80x9cSemiconductor Processing Method of Forming Field Effect Transistorsxe2x80x9d.
U.S. Patent Application No. 20020130377 A1 published Sep. 19, 2002 of Khare et al., which is commonly assigned, entitled xe2x80x9cMethod For Improved Plasma Nitridation of Ultra Thin Gate Dielectricsxe2x80x9d describes xe2x80x9cforming a gate dielectric for an integrated circuit device . . . forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.xe2x80x9d It is stated that xe2x80x9cNitrogen doping, particularly Remote Plasma Nitridation (RPN), is a known technique for increasing the dielectric constant (and hence the unit capacitance) of silicon oxide dielectrics, a known process of nitriding a gate oxide layer is illustrated.xe2x80x9d In addition it states that xe2x80x9ca silicon substrate . . . is subjected to oxidation, such as by heating the substrate . . . in a oxygenated environment, thereby forming an insulating oxide layer . . . of SiO2 . . . the dielectric performance of the oxide layer becomes increasingly important as gate thicknesses shrink into the deep sub-micron dimensions. In order to improve the dielectric constant of the oxide layer to achieve lower leakage current per unit capacitance, excited nitrogen atoms are introduced into the oxide layer by a process known as Remote Plasma Nitridation (RPN) . . . . As a result of the RPN process, the oxide layer . . . is converted to a silicon oxynitride layer . . . having the general chemical composition SiOxNy . . .xe2x80x9d
The RPN process is a high temperature process which causes problems when using temperature sensitive materials.
U.S. Patent Application No. 20020185675A1, published Dec. 12, 2002, of Furukawa, which is commonly assigned, entitled xe2x80x9cSOI Device With Reduced Junction Capacitance xe2x80x9d describes an example of formation of a gate dielectric which xe2x80x9cis silicon oxynitride formed by thermal oxidation followed by nitridation of the oxide by remote plasma nitration (RPN) or decoupled plasma nitridation (DPNxe2x80x9d
U.S. Patent Application No. 20030100155 A1, published May 29, 2003 of Lim et al. entitled xe2x80x9cMethod for Fabricating Semiconductor Devices Having Dual Gate Oxide Layers xe2x80x9d describes a selective DPN xe2x80x9cdecoupled treatmentxe2x80x9d process comprising a xe2x80x9cmethod for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.xe2x80x9dThe DPN treatment is employed for the xe2x80x9ccell region Ixe2x80x9d, but is not employed in the xe2x80x9cperipheral circuit region IIxe2x80x9d. While the cell region I and the peripheral circuit region II are differentiated, Lim et al. does not contemplate the concept of differentiation of CMOS NFET and PFET areas. Lim et al discloses a method of generating different gate dielectric thickness in a cell vs. peripheral regions of the chip, which will generate the same gate dielectric for NFET and PFET within each of the respective areas, while the method of the present invention separates NFET and PFET (which will have the same thickness). Multiple gate dielectric thicknesses on a single chip are quite common in the industry. For example, one might have a 15 xc3x85, 30 xc3x85, 70 xc3x85 gate dielectric on a single chip. However, within each dielectric thickness, the gate dielectric composition and thickness is the same for the NFET and the PFET dielectric layers, which is an industry standard.
The DPN process is a low temperature process, which avoids problems when using temperature sensitive materials.
In the Trivedi patent 6,541,395, nitrogen (N) is added to PFET gate dielectric layers for reduction of boron penetration, with no nitrogen (N) added to NFET gate dielectric layers. The electrical properties of the gate dielectric layers are much different between 5-20 xc3x85 (the preferred range of the present invention) and 30-50 xc3x85(the preferred range of Trivedi et al.). Leakage reduction by increasing nitrogen concentration is typically observed only when the silicon oxide is below about 20 xc3x85. The Trivedi et al. patents appear to be targeted at a much thicker oxide than the present invention. The reason Trivedi et al. puts N into the gate oxide of the PFET is that the addition of N to the gate oxide forms an oxynitride, which tends to block boron diffusion. That has the benefit of reducing boron penetration from the P+ polysilicon gate electrode into the channel of the PFET. In the sub 20 xc3x85thickness range, gate leakage is reduced by oxynitride relative to pure SiO2 for both NFET and PFET devices. Hence the present invention places N in both NFET and PFET gate dielectric layers.
The Trivedi et al. patents employ growth of nitrided silicon oxide first, resist masking and HF etch and growth of second (nitrogen-free) silicon oxide. The first silicon oxide is always thicker, since it is exposed to a second (nitrogen-free) oxide. Because the Trivedi et al. patents relate to a higher temperature thermal process, the processes described thereby will always result in a thicker second silicon oxide (thinner oxynitride for PFET and thicker SiO2 for NFET). The thicker oxide on the NFET has the negative effect of reducing the transistor drive current. The present invention provides a means of creating oxides by employing a low temperature plasma which can eliminate the increase in physical thickness seen in high temperature oxidation as disclosed by the Trivedi et al. patents. Hence the present invention can achieve the same physical thickness in both NFET and PFET gate dielectric layers (avoiding the problem of reduced transistor current caused by the fact that any physical thickness increase decreases transistor current), while achieving different levels nitrogen concentration in the two different areas of a CMOS device, i.e. the NFET gate dielectric layers and the PFET gate dielectric layers.
With reference to Lim et al, a first very significant difference is that the present invention is based upon our discovery that the optimum composition of an NFET gate dielectric layer is different from the optimum composition of a PFET gate dielectric layer. This fact is not generally known, and we discovered it only through many experiments. Secondly, once we learned the above fact, we realized that it is highly desirable to generate different oxynitride concentration NFET and PFET gate dielectric layers to fully optimize CMOS performance. The present invention employs the use of a low temperature process such as DPN with the combination of a soft photoresist mask to achieve this enhanced result.
Distinguishing features of the present invention are as follows:Room temperature plasma enables use of a photoresist soft mask in patterning of the regions being treated with nitridation.
Nitrogen is introduced into both PFET and NFET areas (an additional area could include a decoupling capacitor with a capacitor dielectric layer which has been subjected to intense nitridation).
Nitrogen in NFET is beneficial for gate leakage reduction, but degrades mobility when the N concentration is too high.
Nitrogen in PFET reduces gate leakage/boron penetration, improves mobility. The combination of the previous two facts (which is not generally known) leads one to want to optimize PFET and NFET gate oxide separately.
The same base oxide is used for both NFET and PFET areas with nitrogen being optimized separately. Sample: areal N dose for NFET=0.8E15 to 1.2E15 cmxe2x88x922, N dose for PFET=1.5E15 to 2.5E15 cm2. This configuration can be reversed depending on the application and desired results. This is merely an example that we have found to be particularly beneficial and preferred for methods of manufacture in accordance with our invention and products of those methods.